Intel announced the official name of the processor, Itanium, on October 4, 1999.
Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development.
Thus Intel and HP partnered in 1994 to develop the IA-64 ISA, using a variation of VLIW design concepts which Intel named explicitly parallel instruction computing (EPIC).
The first Itanium processor, codenamed Merced, was released in 2001.
The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel.
It has a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s.
With Quick Path, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs.
During this time, HP had begun to believe that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors.
Intel had also been researching several architectural options for going beyond the x86 ISA to address high end enterprise server and high performance computing (HPC) requirements.
This contrasts with other superscalar architectures, which depend on the processor to manage instruction dependencies at runtime.
In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle.
HP and Intel brought the next-generation Itanium 2 processor to market a year later. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem.